Jung Kyu Chae

Jung Kyu Chae

Core Qualifications ---------------------------------------------------------------------------------------------- Hardware Engineering: Design Technology Co-optimization for advanced nodes (5nm and beyond, Gate-all-around) - Technology definitions, Standard cell architecture design,... | South Korea

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Work Experience

Intel

Senior Foundry Product Engineer, Ph.D. (Design Flow / Ppa / Dtco Expert)

Sun Aug 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Samsung Electronics

Staff Engineer, Ph.D. (Dtco Engineer)

Sat Sep 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jul 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)

Imec

Senior R&D Engineer, Ph.D. (Dtco Engineer)

Sun Oct 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Aug 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)

Lg Electronics

Senior R&D Engineer, Ph.D. (Standard Cell Designer)

Mon Sep 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Aug 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)

Stmicroelectronics

Cad Engineer, Ph.D. Candidate (R&D Engineer)

Tue Mar 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jun 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)

Lip6

Analog Circuit Designer (Intern)

Thu Apr 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Dec 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)

Isdl

Custom Layout Designer (Intern)

Wed Apr 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jun 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)

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